1. Field of the Invention
The present invention relates to a maximum/minimum value determination apparatus for determining a maximum/minimum value between two digital signals especially used in image processing field. With the maximum/minimum value determination apparatus of the present invention, the amount of the transistors configured as a comparator for determining a maximum/minimum value can be considerably reduced, so is the size of the related IC chip which is integrated by the transistors.
2. Description of the Prior Art
An image processing technique applied in the digital integration circuit normally utilizes a comparator to compare different digital signals and then selects one from the digital signals according to the compared result. FIG. 5 illustrates a conventional circuit used to compare two digital signals and select a maximum/minimum one from the two. This conventional circuit comprises a binary comparator 50 and two multiplexers 60 and 70 which are connected to the binary comparator 50. The binary comparator 50 can determine the larger one of two digital signals A and B. When the digital signal B is greater than or equal to digital signal A, the binary comparator 50 outputs a high level signal (hereinafter simplified as "1"), otherwise a low level signal (hereinafter simplified as "0"). The output signal from the comparator 50 is used to be a selecting signal OUT for the two multiplexers 60 and 70. The multiplexer 60 outputs the maximum one of the two signals A and B according to the selecting signal OUT from the comparator 50. Specifically, when the selecting signal OUT is "1" the multiplexer 60 selects (outputs) the signal B, and when the selecting signal OUT is "0" the multiplexer 60 selects (outputs) the signal A. Similarly, the multiplexer 70 selects (outputs) the minimum one of the two signals A and B according to the selecting signal OUT from the comparator 50.
Although the above configuration can determine the maximum and the minimum one of two digital signals A and B, the cost thereof is relatively high due to too many transistors being required in an IC chip of the binary comparator. For example, in a 4-bit binary comparator 54 as shown in FIG. 6, many logic gates constituted by 48 transistors are required. This structure is too complicated and the chip size is relatively large.
It is requisite to provide a new structure which can determine maximum/minimum values with simplifier configuration and reduced size of the related IC chip.